Impedance-based fault location algorithms have become an industry standard in modern microprocessor based protection relays. The reason for their popularity is their easy implementation as they utilize the same signals as other functions. Their performance has proven to be quite satisfactory in localizing short-circuit faults in transmission lines. Nowadays impedance-based fault location is becoming an increasingly common feature also in distribution voltage level relays. Distribution networks, however, have specific features which further complicate and challenge fault localization algorithms. These include e.g. presence of laterals and load taps, which deteriorate fault location accuracy.
One important factor affecting the accuracy of impedance-based fault localization algorithms is the combined effect of load current and fault resistance. A majority of prior art fault localization algorithms try to eliminate the load component from measured currents. The most commonly implemented fault location algorithms are based on the so-called Takagi method [see e.g. document Impedance-based Fault Location Experience, Karl Zimmerman and David Costello, Schweitzer Engineering Laboratories, Inc., USA]. Takagi method uses delta quantities (fault state value minus healthy state value) for load compensation. The algorithm further assumes that the load is tapped to the end point of the electric line (e.g. a feeder); i.e. the fault is always located in front of the load point. This may be an adequate assumption in high-voltage transmission lines, but in real medium voltage feeders this assumption is rarely correct. In fact, due to voltage drop considerations, loads are typically located either at the beginning of the feeder or distributed more or less randomly over the entire feeder length. In such cases, the accuracy of prior art fault localization algorithms is deteriorated.